DEPARTMENT OF CS & IT

CS 021 EMBEDDED SYSTEMS

 

SYLLABUS

UNIT I 

Introduction to Embedded Systems: Characteristics , Classification and

Requirements

UNIT II

Timing and Clocks in Embedded Systems, Task modelling and management and

Real-time operating system issues

UNIT III

Signals: Frequency Spectrum, Sampling, Digitization, Signal conditioning and

processing.

Modelling and characterization of embedded computing systems

UNIT IV

Embedded Control: Control hierarchy, Communication Strategies for Embedded

Systems.

Encoding and Flow Control.

UNIT V

Fault Tolerance, Formal Verification.

REFERENCES

1.  H Kopetz "Real-Time Systems in Distributed Systems"

2.  Prof. D. D. Kinikar "Lecture Notes"

3. R. K. Gupta "Co-Synthesis of Hardware and Software"

OTHER REFERENCES:

1. Dr. Raj Kamal "Embedded Systems"

2.  Wayne Wolf  "Computers as components - Principles of embedded computing system design"

3. Jean J. Labrosse "Embedded Systems"

4. Peter Marwedel

5. C.M. Krishna and Kang G. Shin " Real-Time Systems"

6. Stuart Bennett " Real-time Computer Control"

7. Jane W. S. Liu " Real-Time Systems"

8. Joseph Coutlis "Embedded Hardware Design"

9. "Signals and Systems"

10. "Process Instrumentation Control Technology" Johnson

Magazines

1. Electronics For You September 2004 "Embedded Systems"

2. IEEE Computer April 2003 "Hardware CODESIGN Software"

3. Embedded Computing

Web Links

1.http://mesi.ucsd.edu/gupta/cse2379.html

2. http://www.dspguide.com [DSP book Steven W. Smith Ph.D ]

3. http://www.embedded.com

NOTES

Unit I

Introduction to Embeddeds Systems [R K Gupta] 

Characteristics

Unit II

Timing and Clocks I [R K Gupta]  Timing and Clocks II [H Kopetz]

Tasks modelling and Task Management [R K Gupta]

Real-Time Operating System Issues

Unit III

Signals

Frequency Spectrum I    II    III     IV  V     VI   VII  VIII

Digitization ADC and DAC

Modeling I  II

Unit IV

Controls I  II  III  IV

Communication I   II   III   IV

Encoding

Flow Control

Unit V

Fault Tolerance I   II  III  IV

Formal Verification I  II   III  IV  V  VI  VII